A common architecture of a computerized device includes one or more input/output ports, one or more electronic boards (cards), and one or more local buses. The one or more local buses can be used as backplanes for connecting the plurality of boards among themselves and with the input/output ports. Generally, some boards may have one or more of their own local buses for connecting integrated circuits on the card between themselves and an external port of the board. Exemplary integrated circuits include microprocessors, Digital Signal Processors (DSP), FPGA, ASIC, etc. As used herein, the terms “DSP”, “integrated circuits”, “computing devices”, “microprocessor”, “ASIC” and “FPGA” can be interchangeable. For example, the term ‘DSP’ may be used as a representative term for any of the above group. On some boards, one or more local buses may transfer data directly, or almost directly, to/from the DSPs themselves. As used herein, the term bus refers to any type of communication link between devices. A bus can be a point to point connection, a multipoint to multipoint, a network, etc.
Several types of technologies can be used for implementing buses. One common method is using a Time Division Multiplex (TDM), in which each element on the bus has a time slot on which the element can transmit its data. An alternate mode is using an addressable bus in which sending the information is done in cells, also known as packets, burst, transaction, chunk of data, etc. As used herein, the term ‘cell’ refers to any of the above group.
In addressable bus architecture, each element on the bus has its own address. Each cell has a header and a payload. Usually the header includes at least a destination address to which the cell is targeted and the payload includes the transmitted data. Only an element that is associated with the destination address can retrieve the cell from the local bus. Exemplary addressable buses include Peripheral Component Interconnect (PCI) bus, PCI extended (PCI-X), and Industry Standard Architecture bus (ISA).
The efficiency of an addressable bus is higher than TDM buses. Therefore, more and more DSPs are using addressable buses. However, common addressable buses may have some inefficiency affecting certain applications. One of the drawbacks of an addressable bus is the inability to transmit a cell in a multicast mode to a group of destination devices. In a conventional addressable bus, a cell that has to be transmitted to a group of elements (multicast) is transmitted once for each destination in the group. Accordingly, system efficiencies are lost because system resources are used to continuously transmit the same cell of data.
Some prior art methods have been proposed for overcoming the inefficiency of multicasting over an addressable bus by using a multicast address as a destination address and a switch having a translating table for translating the multicast address to the relevant group of addresses. The switch replicates the received data (the payload) and transmits it to the group of addresses. However, these methods are difficult to manage because both the source of the cell and the switch must be familiar with the multicast addresses. When the multicast group changes, updating the multicast addresses at both the sources and switches is complicated to manage. Such a solution is not suited to applications that have frequent changes in multicast groups during an ongoing session such as multimedia multipoint conferences, in which speakers frequently change. In addition, in such applications certain streams of data can be distributed to more than one multicast group or some destinations may belong to two or more multicast groups. Therefore, managing associations and changes in the associations between multicast address and the private addresses of each element in the group is complicated.
Additionally, each DSP may run two or more processes (logical modules) in parallel. Usually each process may be identified by associating it with a certain address or a space of addresses in the internal memory of the DSP. Consequently, although a DSP is a single element on the bus, the DSP may have more than one address.
Furthermore, there are applications in which a size of a cell is smaller than the size of a data frame that has to be transferred between two nodes and thus the data frame must be transmitted in two or more cells. Ideally, the data frame is transmitted in consecutive cells to simplify the reconstruction of the data frame at the receiver end (in a relevant addresses space of a memory of a DSP, for example). In audio or video application, for example, a common frame of data that is transferred over a local bus can be bigger than a cell. Due to the standards of the local bus, the bus may be switched from one source of data to another source before all of the cells carrying an entire data frame from the first source can be transmitted. In case that the other source of data transmits a cell to the same destination, the data frame from the first source may be received non-sequentially, which may create problems in resuming the frame.
Accordingly, there is a need in the art for more efficient processes for transmitting multicast cells over an addressable bus wherein multicast groups frequently change during a session. Ideally, the process should be easy to manage and adapted to carry streams of data that are bigger than a common cell. Such a method would be ideally suited for multimedia multipoint conferencing systems, among other applications.